View WM2633_3937655.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

WM2633 byte-wide parallel input, 12-bit voltage output dac with internal reference production data, july 1999, rev 1.0 wolfson microelectronics ltd lutton court, bernard terrace, edinburgh, eh8 9nx, uk tel: +44 (0) 131 667 9386 fax: +44 (0) 131 667 5176 email: sales@wolfson.co.uk http://www.wolfson.co.uk production data contain final specifications current on publication date. supply of products conforms to wolfson microelectronics? terms and conditions. masterrev1.0.doc 07/15/99 3:52 ? 1999 wolfson microelectronics ltd . features ? 12-bit voltage output dac ? dual supply 2.7v to 5.5v operation ? dnl 0.3 lsbs, inl 1.2 lsbs ? internal programmable voltage reference ? programmable settling time ? 8-bit micro controller compatible interface ? power down mode (10na) applications ? battery powered test instruments ? digital offset and gain adjustment ? battery operated/remote industrial controls ? machine and motion control devices ? wireless telephone and communication systems ? speech synthesis ? arbitrary waveform generation ordering information device temp. range package WM2633cdt 0 to 70 c 20-pin tssop WM2633idt -40 to 85 c 20-pin tssop description the WM2633 is a 12-bit voltage output, resistor string, digital- to-analogue converter. a hardware controlled power down mode is provided that reduces current consumption to 10na. the WM2633 features an internal programmable voltage reference simplifying overall system design. a reference voltage may also be supplied externally. the device has an 8-bit microcontroller compatible parallel interface. the eight data lsbs, the four data msbs, and the five control bits are written using three different addresses. excellent performance is delivered with a typical dnl of 0.3 lsbs and a typical inl of 1.2 lsbs. the output stage is buffered by a x2 gain near rail-to-rail amplifier, which features a class a output stage (slow mode, class ab). the settling time of the dac is software or pin programmable to allow the designer to optimise speed versus power dissipation. the device is available in a 20-pin tssop package. commercial temperature (0 to 70c) and industrial temperature (-40 to 85c) variants are supported. block diagram typical performance (13) out d[0-7] (19,20, 1-6) 3-bit control latch ref(12) power-on reset nwe (17) (14) gnd reference input buffer WM2633 dac output buffer ncs (18) a[0-1] (8, 7) 4-bit dac msw holding latch 8-bit dac lsw holding latch x1 powerdown/ speed control x2 (16) nldac parallel interface and control logic spd (9) npd (15) 12-bit dac latch dvdd (10) avdd (11) 2-bit reference select latch 1.024v/2.048v selectable reference x1 reference output buffer with ouput enable avdd = dvdd 5v, v ref = external. 2.048v, speed = fast mode, load = 10k/100pf -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 512 1024 1536 2048 2559 3071 3583 4095 digital code dnl - lsb
WM2633 production data wolfson microelectronics ltd pd rev 1.0 july 1999 2 pin configuration 9 10 spd dvdd 12 11 ref avdd 20 13 14 15 16 17 18 19 d1 agnd npd nldac nwe ncs d0 out 8 1 2 3 4 5 6 7 a0 d3 d4 d5 d6 d7 a1 d2 pin description pin no name type description 1 d2 digital input data input. 2 d3 digital input data input. 3 d4 digital input data input. 4 d5 digital input data input. 5 d6 digital input data input. 6 d7 digital input data input. 7 a1 digital input address input. 8 a0 digital input address input. 9 spd digital input speed select. digital input. 10 dvdd supply digital positive power supply. 11 avdd supply analogue positive power supply. 12 ref analogue i/o analogue reference voltage input/output. 13 out analogue output dac analogue voltage output. 14 gnd supply ground. 15 npd digital input power down. active low digital input which powers down all analogue circuits. 16 nldac digital input load dac. digital input active low. nldac must be taken low to update the dac latch from the holding latches. 17 nwe digital input write enable. digital input active low. 18 ncs digital input chip select. digital input active low. 19 d0 digital input data input. 20 d1 digital input data input.
production data WM2633 wolfson microelectronics ltd pd rev 1.0 july 1999 3 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. condition min max digital supply voltages, avdd or dvdd to gnd 7v supply voltage differences, avdd to dvdd -2.8v 2.8v reference input voltage -0.3v avdd + 0.3v digital input voltage range to gnd -0.3v dvdd + 0.3v operating temperature range, t a WM2633cdt WM2633idt 0 c -40 c 70 c 85 c storage temperature -65 c 150 c lead temperature 1.6mm (1/16 inch) soldering for 10 seconds 260 c recommended operating conditions parameter symbol test conditions min typ max unit supply voltage avdd, dvdd 2.7 5.5 v high-level digital input voltage v ih see note 1 2 v low-level digital input voltage v il see note 1 0.8 v reference voltage to ref v ref see note 1 avdd - 1.5 v load resistance r l 2k ? load capacitance c l 100 pf WM2633cdt 0 70 c operating free-air temperature t a WM2633idt -40 85 c note: reference input voltages greater than avdd/2 will cause saturation for large dac codes.
WM2633 production data wolfson microelectronics ltd pd rev 1.0 july 1999 4 electrical characteristics test characteristics : r l = 10k ? , c l = 100pf avdd = dvdd = 5v 10%, v ref = 2.048v and avdd = dvdd = 3v 10%, v ref = 1.024v over recommended operating free-air temperature range (unless noted otherwise). parameter symbol test conditions min typ max unit static dac specifications resolution 12 bits integral non-linearity inl see note 1 1.2 3 lsb differential non-linearity dnl see note 2 0.3 0.5 lsb zero code error zce see note 3 12 mv gain error ge see note 4 0.3 % fsr d.c power supply rejection ratio d.c. psrr see note 5 0.5 mv/v zero code error temperature coefficient see note 6 20 ppm/ c gain error temperature coefficient see note 6 20 ppm/ c dac output specifications output voltage range 0 avdd- 0.4 v output load regulation 2k ? to 10k ? load see note 7 0.1 0.3 % power supplies active supply current idd no load, v ih =dvdd, v il =0v avdd = dvdd = 5v, v ref = 2.048v, internal slow fast avdd = dvdd = 5v v ref = 2.048v, external slow fast avdd = dvdd = 3v, v ref = 1.024v, internal slow fast avdd = dvdd = 3v, v ref = 1.024v, external slow fast see note 8 1.3 2.3 0.9 1.9 1.2 2.1 0.9 1.8 1.6 2.8 1.2 2.4 1.5 2.6 1.1 2.3 ma ma ma ma ma ma ma ma power down supply current no load, all inputs 0v or dvdd see note 9 0.01 1 a dynamic dac specifications slew rate dac code 32-4095, 10%-90% slow fast see note 10 1.2 6 1.7 10 v/ s v/ s settling time dac code 32-4095 slow fast see note 11 3.5 1 s s
production data WM2633 wolfson microelectronics ltd pd rev 1.0 july 1999 5 test characteristics : r l = 10k ? , c l = 100pf avdd = dvdd = 5v 10%, v ref = 2.048v and avdd = dvdd = 3v 10%, v ref = 1.024v over recommended operating free-air temperature range (unless noted otherwise). parameter symbol test conditions min typ max unit glitch energy code 2047 to code 2048 5 nv-s signal to noise ratio snr f s = 480ksps, f out = 1khz bw = 20khz, ta=25 c see note 12 73 78 db signal to noise and distortion ratio snrd f s = 480ksps, f out = 1khz bw = 20khz, ta=25 c see note 12 61 67 db total harmonic distortion thd f s = 480ksps, f out = 1khz bw = 20khz, ta=25 c see note 12 -69 -62 db spurious free dynamic range spfdr f s = 480ksps, f out = 1khz bw = 20khz, t a = 25 c see note 12 63 74 db reference configured as input reference input resistance rref 10 m ? reference input capacitance cref 55 pf reference feedthrough v ref =1v pp at 1khz + 1.024v d.c., dac code 0 -60 db reference input bandwidth v ref = 0.2v pp + 1.024v d.c. dac code 2048 slow fast 500 900 khz khz reference configured as output low reference voltage v refoutl 1.003 1.024 1.045 v high reference voltage v refouth vdd > 4.75v 2.027 2.048 2.069 v output source current i refsrc 1ma output sink current i refsnk -1 ma load capacitance 100 pf psrr -48 db digital inputs high level input current i ih input voltage = dvdd 1 a low level input current i il input voltage = 0v -1 a input capacitance c i 8pf notes : 1. integral non-linearity (inl) is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full scale errors). 2. differential non-linearity (dnl) is the difference between the measured and ideal 1lsb amplitude change of any adjacent two codes. a guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. zero code error is the voltage output when the dac input code is zero. 4. gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. power supply rejection ratio is measured by varying avdd from 4.5v to 5.5v and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. zero code error and gain error temperature coefficients are normalised to full scale voltage. 7. output load regulation is the difference between the output voltage at full scale with a 10k ? load and 2k ? load. it is expressed as a percentage of the full scale output voltage with a 10k ? load.
WM2633 production data wolfson microelectronics ltd pd rev 1.0 july 1999 6 8. i dd is measured while continuously writing code 2048 to the dac. for v ih < dvdd - 0.7v and v il > 0.7v supply current will increase. 9. typical supply current in powerdown mode is 10na. production test limits are wider for speed of test. 10. slew rate results are for the lower value of the rising and falling edge slew rates. 11. settling time is the time taken for the signal to settle to within 0.5lsb of the final measured value for both rising and falling edges. limits are ensured by design and characterisation, but are not production tested. 12 . snr, snrd, thd and spfdr are measured on a synthesised sinewave at frequency f out generated with a sampling frequency f s . parallel interface d[0-7] a[0-1] ncs nwe nldac data x x address x x t sud t hd t sua t sucswe t wwe t suweld t wld t ha figure 1 timing diagram symbol test conditions min typ max unit t sucswe setup time ncs low before positive nwe edge 15 ns t sud data ready before positive nwe edge 10 ns t hd data hold after positive nwe edge 5ns t sua setup time for address bits a0, a1 20 ns t suweld positive nwe edge before nldac low 5ns t wwe high pulse width of nwe 20 ns t wld low pulse width of nldac 23 ns
production data WM2633 wolfson microelectronics ltd pd rev 1.0 july 1999 7 typical performance graphs avdd = dvdd = 5v, v ref = external. 2.048v, speed = fast mode, load = 10k/100pf -3 -2 -1 0 1 2 3 0 512 1024 1536 2048 2559 3071 3583 4095 digital code inl - lsb figure 2 integral non-linearity 0 0.5 1 1.5 2 2.5 3 00.511.522.533.54 isink - ma vo - output voltage - v slow fast avdd = dvdd = 3v, v ref = internal. 1v, input code = 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 00.511.522.533.54 isink - ma vo - output voltage - v slow fas) avdd = dvdd = 5v, v ref = int. 2v, input code = 0 figure 3 sink current avdd = 3v figure 4 sink current avdd = 5v 2.035 2.0355 2.036 2.0365 2.037 2.0375 2.038 2.0385 2.039 2.0395 00.511.522.533.54 isource - ma vo - output voltage - v slow fast avdd = dvdd = 3v, v ref = int. 1v, input code = 4095 4.075 4.0755 4.076 4.0765 4.077 4.0775 4.078 4.0785 4.079 4.0795 00.511.522.533.54 isource - ma vo - output voltage - v slow fast avdd = dvdd = 5v, v ref = int. 2v, input code = 409 5 figure 5 source current avdd = 3v figure 6 source current avdd = 5v
WM2633 production data wolfson microelectronics ltd pd rev 1.0 july 1999 8 device description general function the device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see block diagram). the output voltage is determined by the reference input voltage and the input code according to the following relationship: output voltage = () 4096 code v 2 ref input output 1111 1111 1111 () 4096 4095 v 2 ref :: 1000 0000 0001 () 4096 2049 v 2 ref 1000 0000 0000 () ref ref v 4096 2048 v 2 = 0111 1111 1111 () 4096 2047 v 2 ref :: 0000 0000 0001 () 4096 1 v 2 ref 0000 0000 0000 0v table 1 binary code table (0v to 2v ref output), gain = 2 power on reset an internal power-on-reset circuit resets the dac register to all 0s on power-up. buffer amplifier the output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2k ? load with a 100pf load capacitance. external reference if an external reference is selected, the reference voltage input is buffered which makes the dac input resistance independent of code. the ref pin has an input resistance of 10m ? and an input capacitance of typically 55pf. the reference voltage determines the dac full-scale output. hardware configuration options the device has three configuration options that are controlled by device pins. device power down the device can be powered-down by pulling pin npd (pin 15) high. this powers down the dac. this will reduce power consumption significantly. the npd pin low overrides the software control bit pwr. when the power down function is released the device reverts to the dac code set prior to power down. settling time the settling time of the device can be controlled by pin spd (pin 9). a one on pin spd will ensure a fast settling time; a zero will ensure a slow settling time. the spd pin high overrides the software control bit spd. simultaneous dac update the nldac pin (pin 16) can be held high to prevent word writes from updating the dac latch. by writing the new value to the dac then pulling nldac low, the new dac code is loaded into the dac latch.
production data WM2633 wolfson microelectronics ltd pd rev 1.0 july 1999 9 parallel interface the device latches data on the positive edge of nwe. it must be enabled with ncs low. whether the data is written to one of the dac holding latches (msw, lsw) or the control register, depends on the address bits a1 and a0. nldac low updates the dac with the value in the holding latch. nldac is an asynchronous input and can be held low, if a synchronous update is not necessary. alternatively, the rldac bit of the control register can be used to synchonously update the dac latch via software control. d[0-7] a[0-1] ncs nwe nldac x msw lsw xx 10 xx figure 7 example of a complete write cycle using nldac to update the dac d[0-7] a[0-1] ncs nwe nldac x msw lsw x 01 x control x x x 3 x x figure 8 example of a complete write cycle using the control word to update the dac . if nldac is held high as shown above, the dac latch is normally closed, but can be made transparent by setting the rldac control register bit high. the procedure shown assumes that the rldac bit is low at the start and is written high on the final write.
WM2633 production data wolfson microelectronics ltd pd rev 1.0 july 1999 10 software configuration options data format the wm2613 writes data either to one of the dac holding latches or to the control register depending on the address bits a1 and a0. a1 a0 latch d7d6d5d4d3d2d1d0 00 dac lsw holding dac 7 dac 6 dac 5 dac 4 dac 3 dac2 dac 1 dac 0 01 dac msw holding x x x x dac 11 dac 10 dac 9 dac 8 10 reserved 00000000 11 control x x x ref1 ref0 rldac pwr spd table 2 register map programmable settling time settling time is a software selectable 3.5 s or 1 s, typical to within 0.5lsb of final value. this is controlled by the value of spd ? bit d12. a one defines a settling time of 1 s, a zero defines a settling time of 3.5 s. pin bit spd spd mode 00slow 01fast 10fast 11fast table 3 programmable settling time programmable power down the power down function can be controlled by pwr. a zero configures the device as active, or fully powered up, a one configures the device into power down mode. when the power down function is released the device reverts to the dac code set prior to power down. pin bit npd pwd power 00down 01down 10normal 11down table 4 programmable power down load dac latch bit rldac controls the function of the dac latch. a one configures the dac latch as transparent. a zero configures the dac latch to be controlled by pin nldac. pin bit nldac rldac latch 0 0 transparent 0 1 transparent 10hold 1 1 transparent table 5 load dac latch
production data WM2633 wolfson microelectronics ltd pd rev 1.0 july 1999 11 programmable internal reference the reference can be sourced internally or externally under software control. if an external reference voltage is applied to the ref pin, the device must be configured to accept this. if an external reference is selected, the reference voltage input is buffered which makes the dac input resistance independent of code. the ref pin has an input resistance of 10m ? and an input capacitance of typically 55pf. the reference voltage determines the dac full-scale output. if an internal reference is selected, a voltage of 1.024v or 2.048 is available. the internal reference can source up to 1ma and can therefore be used as an external system reference. ref1 ref0 referencce 0 0 external (default) 0 1 1.024v 1 0 2.048v 1 1 external table 6 programmable internal reference
WM2633 production data wolfson microelectronics ltd pd rev 1.0 july 1999 12 package dimensions c l gauge plane 0.25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.25mm. d. meets jedec.95 mo-153, variation = ac. refer to this specification for further details. dm008.c dt: 20 pin tssop (6.5 x 4.4 x 1.0 mm) symbols dimensions (mm) min nom max a ----- ----- 1.20 a 1 0.05 ----- 0.15 a 2 0.80 1.00 1.05 b 0.19 ----- 0.30 c 0.09 ----- 0.20 d 6.40 6.50 6.60 e 0.65 bsc e 6.4 bsc e 1 4.30 4.40 4.50 l 0.45 0.60 0.75 0 o ----- 8 o ref: jedec.95, mo-153 a a2 a1 seating plane -c- 0.05 c 11 20 e1 e e b 10 1 d

▲Up To Search▲

Price & Availability of WM2633

	To Download WM2633 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .